1. Technical Field
The present disclosure relates to a memory device, and in particular, to a memory device configured so as to suppress the bit line leakage current.
2. Description of Related Art
Recently, the existing memory technology faces physical limits in scaling down, such that developing new memory technologies becomes important in the research of the related field.
As the structure of memory array increases in size, a memory device in the array structure is disturbed by the parasitic leakage current, which not only increases the power consumption but also may cause misread when the memory device reads data via the bit lines. Therefore, there is an urgent need to suppress the leakage current on the bit line in the memory device and at the same time to save the area of the memory device in the related field.